1. Field of the Invention
The present invention relates to a non-inverting repeater circuit for use in semiconductor circuit interconnections.
2. Background Art
In developing the transatlantic telegraph and telephone cables, it was found that signals traversing the cable length experienced a transient time degradation. This transient time degradation was found to be proportional to the square of the distance travelled, and was due to the distributed resistance and capacitance along the length of the cable. The problem was solved in cable technology by providing repeater amplifiers every few hundred miles along the cable.
In the development of very large integrated circuit chips, the same problem has been found to occur at much shorter distances. In FIG. 1, there is shown a cross-sectional view of a circuit interconnect 100 connecting a circuit A and a circuit B which are formed in a semiconductor substrate 110. The circuit interconnect 100 is typically formed of a metal (e.g., aluminum), and is insulated from the semiconductor substrate 110 by an oxide layer 120 except where the circuit interconnect 100 is to make contact with the circuit A or the circuit B.
To facilitate a discussion of the transient time degradation problem, the circuit interconnect 100 in FIG. 1 has been indicated as being 4 centimeters long. As a signal from circuit A begins traversing the circuit interconnect 100 toward circuit B, it begins to encounter resistance and capacitance along the length of the line. The resistance is due to the resistivity of the metal line, and is proportional to the length travelled. The capacitance is due to the separation of the circuit interconnect 100 from the semiconductor substrate 110 by the oxide layer 120, and is also proportional to the length travelled. Thus, as the distance a signal travels from circuit A to circuit B along the circuit interconnect 100 doubles, the resistance and capacitance associated with the circuit interconnect 100 also doubles. As the resistance and capacitance are each proportional to the length travelled, the transient time constant .tau..sub.L of the line, which is proportional to both the line resistance and capacitance, is thus proportional to the square of the length travelled.
In the example shown in FIG. 1, the resistance and capacitance encountered up to a distance of 1 centimeter are sufficiently small such that the transient time constant of the line .tau..sub.L is smaller than the transient time constant of the driving circuit .tau..sub.DC. As the transient time constant of the line is smaller, transient time degradation will not be a concern. However, as the signal traverses beyond a distance of 1 centimeter, the overall resistance and capacitance encountered along the line are such that the transient time constant of the line .tau..sub.L quickly becomes greater than the transient time constant of the driving circuit .tau..sub.DC. This in effect means that the rise and fall time associated with the line is greater than the rise or fall time of the driving circuit. As such, the signal traversing the circuit interconnect 100 beyond distances of 1 centimeter is subject to undesirable distortion. As the length traversed is increased, a corresponding increase in distortion of the signal is encountered. Note in FIG. 1 that, for distances less than 1 centimeter, the transient time constant of the line .tau..sub.L is indicated as being smaller than the transient time constant of the driving circuit .tau..sub.DC. In contrast, for distances greater than 1 centimeter, the opposite is true.
It has long been proposed that long circuit interconnect problems on large scale integrated circuit chips be solved the same way that the long telegraph cable problem was solved, i.e. with repeater amplifier circuits. An example of this solution is illustrated in FIG. 2, In FIG. 2, the cross-sectional view shows a circuit interconnect consisting of a number of shorter circuit interconnects 200, 201, 202, and 203, and repeater amplifiers 250, 260, and 270. The circuit interconnects 200, 201, 202, and 203 are also typically formed of a metal (e.g. aluminum), and are shown separated from a semiconductor substrate 210 by an insulating oxide layer 220. The repeater amplifier circuits 250, 260, and 270 are typically semiconductor circuits formed at periodic intervals along the semiconductor substrate 210. The first circuit interconnect 200 interconnects circuit A with the input of a repeater amplifier circuit 250. A second circuit interconnect 201 interconnects the output of the repeater amplifier circuit 250 with the input of the repeater amplifier circuit 260. A third circuit interconnect 202 interconnects the output of the repeater amplifier circuit 260 with the input of the repeater amplifier circuit 270. Finally, the fourth circuit interconnect 203 interconnects the output of the repeater amplifier circuit 270 to the circuit B,
Thus, there is shown a series circuit interconnection of circuit A with circuit B and consisting of the first circuit interconnect 200, the repeater amplifier circuit 250, the second circuit interconnect 201, the repeater amplifier circuit 260, the third circuit interconnect 202, the repeater amplifier circuit 270, and, finally, the fourth circuit interconnect 203. Note that the circuit interconnect 100 as shown in FIG. 1 has been effectively replaced with four shorter circuit interconnects 200, 201, 202, and 203, each being approximately 1 centimeter long in the example shown in FIG. 2.
Turning now to an operational description of the series circuit of FIG. 2, a signal outputted by a circuit A enters and traverses the circuit interconnect 200 to arrive at the input of the repeater amplifier circuit 250. The resistance and capacitance encountered by the signal along the shorter circuit interconnect 200 is sufficiently small, such that the transient time constant of the circuit interconnect 200 .tau..sub.L is smaller than the transient time constant of the driving circuit A .tau..sub.DC. As the transient time constant of the line 200 is typically much less than the rise and fall time of the driving circuit A, transient time degradation of the signal along the line 200 is not a concern. Thus, the repeater amplifier circuit 250 receives a substantially unaffected signal from the circuit interconnection 200 at its input, and provides a repeated output signal at its output. The repeater amplifier circuit 250 then becomes the driving circuit for the signal traversing the second circuit interconnect 201.
As the repeated signal from the repeater amplifier circuit 250 traverses the second circuit interconnect 201, the resistance and capacitance encountered along the shorter circuit interconnect 201 are again sufficiently small such that the transient time constant of the line 201 .tau..sub.L is smaller than the transient time constant of the driving circuit 250 .tau..sub.DC. Thus, it can be seen that the repeater amplifier circuit 260 also receives a substantially unaffected signal which is to be repeated. As similar effect occurs as the signal traverses the remainder of the line. In FIG. 2, note that the transient time constants .tau..sub.L associated with each of the circuit interconnections 200, 201, 202, and 203 are indicated as being smaller than the transient time constant .tau..sub.DC of the driving circuit A and the repeater amplifier circuits 250, 260 and 270, respectively. Thus, in the circuit interconnection and repeater amplifier circuit arrangement of FIG. 2, a signal can leave circuit A and arrive at a circuit B in such a manner that the transient time degradation encountered is not a concern.
In addition, and to meet the duty of disclosure of known prior art which may be material to the present application. Applicant cites the following patents and publication.
In particular, U.S. Pat. No. 4,159,450 issued to Hoover, discloses a complementary class B transistor amplifier stage having a pair of serially connected bipolar transistors in a common collector arrangement in the output circuitry. Also included is a pair of FETs which is connected to receive the input signal and operate as a push-pull driver arrangement to supply an inverted signal current to the common collector arrangement.
U.S. Pat. No. 4,301,383, issued to Taylor, discloses a complementary insulated gate FET buffer with improved bipolar output.
The specification sheet for the Hitachi high speed LS-TTL HG 28 series gate array discloses circuits containing both bipolar and CMOS transistors which represent bi-polar-CMOS gate arrays.
U.S. Pat. No. 4,002,928 issued to Goser et al, discloses an interconnection between two MOS circuits to achieve high speed by utilizing an output stage in the first circuit to transform the signal level to a relatively low level, and an input stage in the second circuit to restore the low signal to a relatively high level.
U.S. Pat. No. 3,818,360, issued to Boutmy et al, discloses a repeater output stage for a bipolar coded signal device having two input terminals receiving signals which are of the same polarity and which are combined to produce a composite bipolar signal.
U.S. Pat. No. 4,499,387, issued to Konishi, discloses a CMOS inverter with two series connected FETs having a variable capacitor connected between the common node of the series transistor connection and a reference voltage, and a voltage generator for providing an output voltage to the variable capacitor to change the capacitance of the variable capacitor.
U.S. Pat. No. 4,424,456, issued to Shiraki et al, discloses a driver circuit for a CCD device and including a CMOS inverter, having a P channel transistor which functions to charge the load capacitance of the CCD device, and a N channel transistor which functions to discharge the equivalent load capacitance. Thus, the N channel and P channel transistors are used to adjust and optimize the charge transfer efficiency of CCD device.
U.S. Pat. No. 4,508,981, issued to Dorler et al, discloses a noise-reducing circuit, to be included in an off-chip driver circuit, for reducing self-induced switching noise in a multi-chip module semiconductor substrate.
U.S. Pat. No. 4,437,022, issued to Miersch et al, discloses an integrated push-pull driver arrangement with reduced noise generation resulting from driver switching.
U.S. Pat. No. 4,419,593, issued to Butler et al, discloses a high speed driver circuit which produces a level shifting between TTL logic levels and high voltage levels necessary to drive CCD devices.
U.S. Pat. No. 4,029,907, issued to Jorgensen et al, discloses an asynchronous digital repeater utilizing amplifiers and multivibrator arrangements to provide a repeater circuit which avoids the problem of responding to the electrical overshoot at the trailing edges of incoming pulses.
U.S. Pat. No. 3,609,479, issued to Hung Chang Lin et al, discloses semiconductor technology improvements allowing improved construction of MIS transistors and bipolar transistors on the same semiconductor substrate. Similarly. U.S. Pat. No. 4,334,196, issued to Schade, discloses vertical and lateral NPN bipolar transistors realized in CMOS technology.
Also of possible relevance, are U.S. Pat. No. 3,898,564 issued to Waldhauer et al, and U.S. Pat. No. 4,210,885 issued to Ho.
In an investigation of the long line transient time degradation problem, a number of features were found to be highly desirable in a repeater amplifier circuit. First, the repeater amplifier circuit should produce a "true" repeated signal rather an inverted signal. Next, the signal delay introduced by the repeater amplifier circuit should be kept at a minimum so it will not become of sufficient magnitude to become a concern. Finally, the repeater amplifier circuit should have high current driving capabilities such that it is capable of driving a highly capacitive load. As the prior art has been deficient in providing a repeater amplifier circuit having these advantages in conjunction, there exists a need for a repeater amplifier circuit having a true repeated output signal, minimum delay, and high current driving capabilities.